When attempting to increase performance for graphics processing units (GPUs), one solution is to apply various techniques to reduce memory bandwidth consumption. Bandwidth reduction is also becoming increasingly important as the performance growth rate for processing power is much larger than performance growth rate for bandwidth and latency for random access memory (RAM).
Texture compression is one popular way of reducing bandwidth requirements. By storing textures in compressed form in memory and transferring blocks of the compressed data over the bus, the texture bandwidth is reduced substantially.
Today, the most used texture compression systems are DXTC [1] for Windows based systems and Xbox, and ETC [2] for mobile handsets. Both these systems divide an image, denoted texture, into texture element (texel) blocks of 4×4 texels and the red, green, blue (RGB) data of the texels is then compressed from (8+8+8)×16=384 bits down to 64 bits. Thus, each texel block is given the same number of bits. This is important since the rasterizer used in the decompression may need to access any part of the texture and needs to easily be able to calculate the memory address of the desired texel block. In other words, a fixed rate codec, i.e. a codec where every texel block takes up the same amount of storage space, is very desirable and is the norm among texture compression algorithms today.
Development of the ETC decoder has resulted in the so called ETC2 decoder [3] having extra functionality for handling the so-called T-mode, H-mode and a PLANAR-mode. The T- and H-mode are designed to handle texel blocks with uneven distribution of color and colors arranged in two groups, respectively. The hardware circuitry of the ETC decoder can be reused to a large extent to encompass the additional T- and H-modes. The PLANAR-mode is, though, quite different from ETC and the T- and H-modes and is designed to handle texel blocks with smooth color transitions. Complex hardware circuitry for the PLANAR-mode would imply that the complexity of the ETC2 decoder would increase significantly as compared to the ETC decoder.
There is, thus, a need for providing an efficient implementation of the PLANAR-mode and in particular such an implementation that can be provided as hardware implementation using a cost efficient circuitry. Such cost efficient circuitry is in particular desirable if the PLANAR-mode is to be used together with the ETC-decoder and the T- and H-modes to form the ETC2 decoder.
A similar problem is generally present within the art, i.e. there is a general need for a technique that can be applied to a decoding system with the purpose of reducing the implementation complexity.